Introduction to Verilog (2.1i)

Cost:
$1500

Software & Version:
2.1i

Audience
Engineers with a desire to learn to effectively use Verilog for modeling, design, and synthesis of digital designs.

Prerequisites
Basic digital design knowledge.

What is the level of the material?
Level II - Intermediate

Training Duration
3 Days

Content Description
This comprehensive course is an effective introduction to the Verilog language with particular emphasis on targeting Xilinx and FPGA devices in general. The information gained here can be applied to any digital design using a Top-Down synthesis design approach. This course is a combination of insightful lecture coupled with practical and interesting lab exercises to reinforce the key concepts.

Objectives
After completing this training, student will be able to:

• Build hardware models using Verilog
• Create top-down designs in Verilog
• Identify how hardware is modeled in Verilog through the use of procedural statements
• Create synthesizable (Register Transfer Level) source code
• Run a behavioral simulation
• Synthesize (compile to hardware) Verilog using Foundation Express
• Run a timing simulation
• Write FPGA optimized code
• Create RTL source files, synthesize, and implement a design in Xilinx FPGA's

Topics or Training Outline

Day 1

• Verilog HDL Introduction
• Hardware Modeling Overview
• Language Concepts
• Verilog Modules & Ports
• Gate Level Modeling
• Operators & Expressions
• Lab Exercises:
  • Write Basic Modules
  • Write Gate Level Model
  • Build Hierarchical Structures with Instantiation

   

  Day 2

• Data-Flow Modeling
• Behavioral Modeling
• Advanced Process Statements
• Verilog Timing Models
• Targeting Xilinx
• Lab Exercises:
  • Write Behavioral Model
  • Write & Compile 4 State-Machine

 

Day 3

• Introduction to the Verilog Testbench
• Tasks & Functions
• Xilinx Synthesis Tools
• Lab Exercises:
  • Build Complex Address Decoder
  • Download & In-circuit Verification of Synthesized Design

References
None

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