Introduction to VHDL (2.1i)

Cost:
$1500

Software & Version:
2.1i

Audience
Engineers with a desire to learn to effectively use VHDL for modeling, design, and synthesis of digital designs.

Prerequisites
Basic digital design knowledge.

What is the level of the material?
Level II - Intermediate

Training Duration
3 Days

Content Description
This comprehensive course is an effective introduction to the VHDL language with particular emphasis on targeting Xilinx and FPGA devices in general. The information gained here can be applied to any digital design using a Top-Down synthesis design approach. This course is a combination of insightful lecture coupled with practical and interesting lab exercises to reinforce the key concepts.

Objectives
After completing this training, student will be able to:

• Build hardware models using VHDL
• Create top-down designs in VHDL
• Identify how hardware is modeled in VHDL through the use of process statements
• Create synthesizable (Register Transfer Level) source code
• Run a behavioral simulation
• Synthesize (compile to hardware) VHDL using Foundation Express
• Run a timing simulation
• Write FPGA optimized code
• Create RTL source files, synthesize, and implement a design in Xilinx FPGA's

Topics or Training Outline

Day 1

• Introduction to VHDL & Hardware Modeling
• Language Concepts
• Signals & Datatypes
• Operators / Expressions
• Concurrent & Sequential Statements
• Lab Exercises:
  • Write Entities
  • Build Hierarchical Structures with Instantiation

   

  Day 2

• Advanced Process Statements
• Behavioral to RTL
• VHDL Timing Models
• Targeting Xilinx
• Lab Exercises:
  • Write Code for 4 State State-Machine
  • Build One Hot Encoded State-Machine

   

  Day 3

• Introduction to the VHDL Testbench
• Functions / Procedures
• Xilinx Synthesis Tools
• Lab Exercises:
  • Build Testbench for Module Verification
  • Download & In-circuit Verification of Synthesized Design

References
None

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