Introduction to Efficient Synthesis & Simulation

Software & Version
Foundation v2.1i or Alliance v2.1i

Audience
New HDL designer who is new to Xilinx.

Prerequisites
Students need to have basic experience with VHDL or Verilog, such as completion of the Verilog CBT. It would be helpful but not required to have experience with HDL Editor.

What is the level of the material?
Level I - Beginning

Training Duration
1 hour plus lab

Content Description
This module focuses on general style guide, not functional elements. Both VHDL and Verilog are discussed.

Objectives
After completing this training, student will be able to:

· Create efficient designs (moderate speed) with respect to the following pics:

• Instantiation vs. inference
• Creating good design hierarchy
• How coding style can affect synthesis results

Topics or Training Outline

Overview of synthesis process
Instantiation vs. inference
Guidelines for hierarchical design
Control structure with parentheses
Getting to know your synthesis tool

Supporting Files
None.

References
support.xilinx.com -> Technical Tips, Xcell, App notes, On-line docs, VHDL and Verilog Reference Guide

Teaching Activities
Structured Discussion x
Paper exercise(s)
Lab exercise(s)
Demo
Review questions x
Test x

Instructor Notes
This module should be combined with Coding for Spartan or Coding for Virtex. Should be coordinated with other HDL coding sections and FPGA Design sections.