Advanced Process Statements with Verilog HDL

Software & Version
N/A

Audience
1-2 year Verilog HDL users, anyone interested in applying Verilog to the design process.

Prerequisites
Basic Verilog HDL, digital design, simulation and design verification concepts.

What is the level of the material?
Level I - Beginning

Training Duration
1 Hour (including review and test)

Content Description
This 'Advanced Process Statements' module explains usage of blocking and non-blocking assignments, delay types and specification, and simulation delta cycles. It also covers use of the casez and casex constructs, in addition to using for or while loops to model functionality.

Objectives
At the completion of this module, students will be able to:

• Write non-blocking assignments for registered logic.
• Write blocking assignments for combinatorial logic.
• Use casez or casex statements when appropriate.
• Discuss the concepts of 'delta' cycles.
• Write for and while loop statement.

Topics or Training Outline:

casez and casex Statements
Loops
Delay Specification
Mixed Blocking/Non-Blocking
Simulator Tasks
Avoiding Inferred Latches

Teaching Activities
Structured Discussion x
Paper exercise(s) x
Lab exercise(s) x
Review questions x
Test x