Behavioral Modeling 2.1i (Verilog)

Software & Version:
2.1i

Audience
New to first year Verilog HDL users, anyone interested in applying Verilog to the design process.

Prerequisites
Basic digital design, simulation and design verification concepts.

What is the level of the material?
Level I - Beginning

Training Duration
1 Hour

Content Description
This 'Behavioral Modeling" module covers usage of Verilog Operators and Expressions, along with the procedural assignment constructs to describe clocked and combinatorial data-flows within always or initial statements. This Module also discusses which constructs are synthesizable and which are not.

Objectives
After completing this training, students will be able to:

• Write an initial statement or block.
• Write an always statement or block
• Define the Verilog concept of procedural assignment.
• Determine when use of 'wire' or 'reg' data-type is appropriate.
• List key Verilog simulator 'Tasks' and 'Directives'
• Write always block using 'event control.'

Topics or Training Outline:

Procedural Statements
Simulator Basics
Concurrency
Blocking/Non Blocking
Event Based Control
If /Else, Case

Teaching Activities
Structured Discussion x
Paper exercise(s) x
Lab exercise(s) x
Review questions x
Test x