Data-Flow Modeling with Verilog HDL

Software & Version:
N/A

Audience
Beginning and first year Verilog HDL users.

Prerequisites
Basic Digital Design.

What is the level of the material?
Level I - Beginning

Training Duration
1 Hour

Content Description
The "Data Flow" module is an introduction into modeling hardware from the
Register Transfer Level (RTL). This section describes how to model a hardware system through the use of "continuous assignments".

Objectives
After completing this training, student will be able to:

• Infer combinatorial logic using the assign construct.
• Use Operators to infer logic & functionality.
• Define the Verilog concept of continuous assignment.
• Determine when use of 'wire' or 'reg' data-type is appropriate

Topics or Training Outline

Define Data Flow
Continuous Assign Statement
Delay Specification (inter-assignment delay)
More on data-types Net (wire) & reg

Supporting Files
None

References
None

Teaching Activities
Structured Discussion x
Paper exercise(s) x
Lab exercise(s) x
Demo
Review questions x
Test