Gate-Level Modeling with Verilog HDL

Software & Version:
2.1i

Audience
New to first year Verilog HDL users, anyone interested in applying Verilog to the design process.

Prerequisites
Basic digital design, simulation and design verification concepts.

What is the level of the material?
Level I - Beginning

Training Duration
1 Hour

Content Description
This 'Gate-Level Modeling' module/unit shows how to use predefined Verilog primitives for low-level hardware modeling. It discussed the gate types, and rules for input/output resolution.

Objectives
After completing this training, students will be able to:

• Write gate-level models.
• Properly declare input and output gates.
• Build wide-gating functions.
• Understand rules for resolving outputs.
• Specify gate-delays for simulation.

Topics or Training Outline:

Gate Types
Signal Resolution
Delays
Syntax Rules

Teaching Activities
Structured Discussion x
Paper exercise(s) x
Lab exercise(s) x
Review questions x
Test x