Hardware Modeling with Verilog HDL

Software & Version:
N/A

Audience
New to first year Verilog HDL users, anyone interested in applying Verilog to the design process.

Prerequisites
Basic digital design, simulation and design verification concepts.

What is the level of the material?
Level I - Beginning

Training Duration
1 Hour (including review and test)

Content Description
This 'Verilog HDL & Hardware Modeling' Module discusses the IEEE 1364 standard and its origination. It discusses how Verilog is used to facilitate 'Top-Down' design description, and 'levels of abstraction' for hardware modeling along with technology specific limitations.

Objectives
At the completion of this Course, students will be able to:

• Discuss the Verilog language origin.
• Define the terms 'Behavioral' and 'RTL'.
• Define the terms 'Inference' and 'Instantiation'.
• Define Hardware Modeling 'Levels of Abstraction'.

Topics or Training Outline

Origin of Verilog
Top Down Design
Levels of Abstraction
Simulation vs. Synthesis
Inference Vs. Instantiation
FPGA Challenges

Supporting Files

Teaching Activities
Structured Discussion x
Paper exercise(s) x
Lab exercise(s) x
Review questions x
Test x