Modules & Ports with Verilog HDL

Software & Version
N/A

Audience
New to first year Verilog HDL users, anyone interested in applying Verilog to the design process.

Prerequisites
Basic digital design, simulation and design verification concepts.

What is the level of the material?
Level I - Beginning

Training Duration
1 Hour (including review and test)

Content Description
This 'Modules & Ports' module discusses the basic unit of logic of logic description, the module. Topics include types and restrictions for port declarations. It covers what declarations may be made within the body of the module.

Objectives
At the completion of this module, students will be able to:

• Declare Verilog module.
• Differentiate between port list & declaration
• Understand when and where 'reg' data-type is allowed.
• Build hierarchy using component instantiation.
• Declare internal signals.
• Map ports on instantiated components.

Topics or Training Outline:

Module Definition
Port Declarations
Mapping Ports
Signals
Hierarchical Structure

Teaching Activities
Structured Discussion x
Paper exercise(s) x
Lab exercise(s) x
Review questions x
Test x