Operators & Expressions with Verilog HDL

Software & Version
N/A

Audience
New to first year Verilog HDL users, anyone interested in applying Verilog to the design process.

Prerequisites
Basic digital design, simulation and design verification concepts.

What is the level of the material?
Level I - Beginning

Training Duration
1 Hour (including review and test)

Content Description
This 'Verilog Operators & Expression' Module/Unit discusses the wide selection of operators available in Verilog. It also shows examples of inferring basic logic & functionality using operators within common expressions. Topics include all operator types.

Objectives
At the completion of this module, students will be able to:

• Write operators using common expressions
• Use 'Logical' and 'Bit-wise' operators in proper context.
• Use 'Relational' and 'Equality' operators
• Discuss classes of operators.
• Control operator precedence.
• Use 'Reduction' operators in hardware modeling.

Topics or Training Outline:

Classes of Operators
Operand Requirements
Writing Expressions
Operator Precedence

Teaching Activities
Structured Discussion x
Paper exercise(s) x
Lab exercise(s) x
Review questions x
Test x