Project Management with
Verilog HDL v2.1i
Software Version
N/A
Audience
1-2 year Verilog HDL users, anyone interested in applying Verilog to the
design process.
Prerequisites
Basic Verilog HDL, digital design, simulation and design verification
concepts.
Training Duration
1 Hour (including review and test)
Content Description
This 'Verilog Design & Project Management' Unit provides suggestions
and guidelines for effective Verilog designs and projects. It discusses
libraries, naming conventions, and designing for reuse. It emphasizes
the individual and collective responsibilities within a design team or
organization.
Objectives
At the completion of this Unit, students will be able to:
- Name signals in consistent,
readable manner.
- Enhance interoperability
of separate design modules.
- Determine appropriate user
interface boundaries for individual and common libraries.
- Partition logic for ease
of integration
Topics or Unit Outline
Signal naming conventions
Designing for re-use.
Managing common libraries.
Enhancing code readability.
Teaching Activities
Structured Discussion x
Paper exercise(s) x
Lab exercise(s) x
Review questions x
Test x
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