Targeting Xilinx with Verilog

Software & Version:
N/A

Audience
Beginning to Intermediate user of Verilog HDL.

Prerequisites
Basic knowledge of Xilinx FPGA's. Intermediate knowledge of Verilog HDL.

What is the level of the material?
Level II - Intermediate X

Training Duration
1 hour

Content Description
"Targeting Xilinx with Verilog" is dedicated to describing the best way of using Verilog-HDL to infer Xilinx FPGA resources. The major "special" resources used in Xilinx FPGA's are described, then implemented either through inference or instantiation.

Objectives
After completing this training, student will be able to:

• Write code to implement an efficient FPGA.
• Instantiate needed resources.
• Infer those resources that are inferrable.

Topics or Training Outline

Architectural Challenge
Dedicated Resources
Inference vs. Instantiation
Tools and Platforms
Coregen & LogiBLOX

Supporting Files
None

References
None

Teaching Activities
Structured Discussion x
Paper exercise(s) x
Lab exercise(s) x
Demo
Review questions x
Test