Tasks & Functions with Verilog HDL

Software & Version
N/A

Audience
1-2 year Verilog HDL users, anyone interested in applying Verilog to the design process.

Prerequisites
Basic Verilog HDL, digital design, simulation and design verification concepts.

What is the level of the material?
Level I - Beginning

Training Duration
1 Hour (including review and test)

Content Description
This 'Tasks & Functions' module shows how Verilog subprograms can be used to modularize code. It covers the application, differences and capabilities of tasks and functions. It shows how subprograms are stored and called -with or without arguments.

Objectives
At the completion of this module, students will be able to:

• Write basic Verilog task.
• Write basic Verilog function.
• Call subprogram within module body.
• Specify arguments for subprogram.

Topics or Training Outline:

Tasks Overview
Function Overview
`Include Usage
Code Modularity

Teaching Activities
Structured Discussion x
Paper exercise(s) x
Lab exercise(s) x
Review questions x
Test x