Testbenches v2.1i (Verilog)

Software & Version
N/A

Audience
1-2 year Verilog HDL users, anyone interested in applying Verilog to the design process.

Prerequisites
Basic Verilog HDL, digital design, simulation and design verification concepts.

What is the level of the material?
Level I - Beginning

Training Duration
1 Hour (including review and test)

Content Description
This 'Testbenches' module teaches concepts of behavioral modeling and verification using the IEEE 1364 standard. It covers how are testbenches are built, instantiation of UUT and internal signals and 'reg' data-types, along with initial and always blocks to create input stimulus. It also covers Verilog simulator tasks and directives.

Objectives
At the completion of this module, students will be able to:

• Write module description for testbench.
• Declare UUT, internal reg and wire data-types.
• Write initial & always blocks for input stimulus.
• Use $monitor or $display tasks to view nodes.

Topics or Training Outline:

Test-Bench Overview
Structure and UUT
Behavioral Modeling
Simulation Basics
$display & $monitor

Teaching Activities
Structured Discussion x
Paper exercise(s) x
Lab exercise(s) x
Review questions x
Test x