Behavioral 2 RTL Coding v2.1i (VHDL)

Software & Version:
N/A

Audience
New and first year VHDL users, anyone considering VHDL for design.

Prerequisites
Basic digital design concepts, schematic capture & simulation flows.

What is the level of the material?
Level II - Intermediate

Training Duration
1 Hour

Content Description
This "Behavioral 2 RTL Coding" demystifies the 'behavioral vs. RTL' coding concept. It makes clear the requirements and procedures for execution (simulation) and synthesis. It gives an example of a system taken from one level to the next. It also discusses issues that impact code portability.

Objectives
After completing this training, student will be able to:

• Complete a 'process' sensitivity list.
• Use explicit 'wait' conditions.
• Write a 'combinatorial' process.
• Write a 'clocked' process.
• Write code for basic state-machine.
• Discuss 'single' versus 'two process' state-machine.

Topics or Training Outline

Synthesis Vs. Simulation
Define Behavioral
Define RTL
Code Portability
Modeling DFF's
State Machines