Concurrent and Sequential Statements v2.1i (VHDL)

Software & Version:
N/A

Audience
0-2 years VHDL experience. Beginners to intermediate users.

Prerequisites
Basic knowledge of VHDL: entity, architecture, rtl, data-types, signals, and process statements.

What is the level of the material?
Level I - Beginning

Training Duration
1 hour

Content Description
Concurrent & Sequential Statements is perhaps the most important module that a student could take to help them in their understanding of how a VHDL process executes in simulation and creates logic in synthesis (the process being the primary unit of logic description). Detailed examples are given and discussed. The idea of concurrent processes is clearly defined and explained - how and when an assignment within a process is executed to eliminate race conditions in simulation and hardware. The concept of delta cycles and their role in simulation are also discussed.

Objectives
After completing this training, student will be able to:

• Write a VHDL process
• Create appropriate wait condition statements
• Determine when signals are updated
• Differentiate between signal 'transactions' and 'events'
• Determine how and when signals are read within the process
• Define the VHDL term 'delta cycle'

Topics or Training Outline

VHDL Process
Transactions & Events
Suspending a Process with explicit or implied 'wait' conditions
Rules for port signals
Rules for assigning to signals in combinatorial or clocked processes

Supporting Files
None

References
None

Teaching Activities
Structured Discussion x
Paper exercise(s)
Lab exercise(s)
Demo
Review questions x
Test