VHDL Methodology: Controlled Operation Statements v2.1i

Software & Version: 
N/A

Audience
New and first year VHDL users, anyone considering VHDL for design.

Prerequisites
Basic digital design concepts, schematic capture & simulation flows.

What is the level of the material?
Level II - Intermediate  

Training Duration
1 Hour

Content Description
This “Controlled Operation Statements” module details VHDL conditional execution hardware models, such as Muxes.  It compares and contrasts the ‘if/else’ and the ‘case’ approach’.  It shows how a ‘for loop’ statement can be used to model repetitive operations which involve array data-structures.

Objectives
After completing this training, student will be able to:

• Write an ‘if/else’ conditional statement.
•  Write an ‘if/else if’ conditional statement.
•  Write an ‘case’ conditional statement.
•  Use the default ‘else’ or ‘others’ clause.
•  Detect and avoid conditions where latches may be inferred.
•  Write ‘for loop’ statements for repetitive operations.

Topics or Training Outline

• Flow Control Statements
•  ‘If Else’ Statements
•  ‘If / Else If’ statements
•   Case Statements
•   Avoiding latch inference
•  ‘For Loop’ statements