Language Concepts v2.1i
(VHDL)
Software & Version:
N/A
Audience
New and first year VHDL users, anyone considering VHDL for design.
Prerequisites
Basic digital design concepts, schematic capture & simulation flows.
What is the level of the
material?
Level II - Intermediate
Training Duration
1 Hour
Content Description
This "Language Concepts" module teaches the basic structure
of VHDL by covering each design unit and their inter-relationship. It
shows syntactical requirements and discusses each stage of compilation
for both behavioral simulation and synthesis.
Objectives
After completing
this training, student will be able to:
- State the VHDL Design Units.
- Write VHDL 'entity' &
'architecture' description
- Build hierarchical units
using instantiation.
- State the four stages of
compilation.
- Instantiate library macro
using component declaration.
- Insert comments in VHDL
code.
- Define a VHDL process.
- Differentiate concurrent
and sequential statements.
Topics or Training Outline
Syntax & Structure
Design Units
Hierarchical Structure
Concurrent Statements
Sequential Statements
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