Operators and Expressions v2.1i (VHDL)

Software & Version:
N/A

Audience
New and first year VHDL users, anyone considering VHDL for design.

Prerequisites
Basic digital design concepts, schematic capture & simulation flows.

What is the level of the material?
Level II - Intermediate

Training Duration
1 Hour

Content Description
This "Operators & Expressions" module covers the most widely used operators for VHDL. It stresses the importance of applying the correct operation for the intended data-type. It also discusses how arithmetic operators use sub-programs for vector manipulation.

Objectives
After completing this training, student will be able to:

• Write standard VHDL expressions.
• Infer logic and functionality using VHDL operators.
• Apply appropriate operators to each data-type.
• Reference appropriate packages for arithmetic functions.
• Use VHDL 'slice' to reference sub-bus structures.
• Use VHDL 'concatenation' operator.

Topics or Training Outline

Logical Operators
Relational Operators
Concatenation
Arithmetic
Sub-Program Usage
Overloaded Operators