Targeting v2.1i (VHDL)

Software & Version:
N/A

Audience
New and first year VHDL users, anyone considering VHDL for design.

Prerequisites
Basic digital design concepts, schematic capture & simulation flows.

What is the level of the material?
Level II - Intermediate

Training Duration
1 Hour

Content Description
This "Targeting" module details how VHDL is applied to a Xilinx or similar device. It explores the necessary trade-off between maximum code portability and device level optimization in the context of popular VHDL EDA tools.

Objectives
After completing this training, student will be able to:

• List Xilinx device-level resources.
• Define which resources can be inferred from code.
• Write statements to instantiate other resources.
• Use FEXP 1.5 constraint editor.
• Generate optimal code for Xilinx devices.

Topics or Training Outline

Architectural Challenge
Dedicated Resources
Inference Vs. Instantiation
Tools & Platforms
Xilinx LogiBlox