Testbenchs v2.1i (VHDL)

Software & Version:
N/A

Audience
New to first year VHDL users, anyone interested in applying VHDL to the design process.

Prerequisites
Basic digital design, simulation and design verification concepts.

What is the level of the material?
Level II - Intermediate

Training Duration
1 Hour

Content Description
This 'VHDL Testbenches" module provides suggestions and guidelines for effective VHDL coding for creating and using testbenches. It demonstrates how any module may be verified by creating a testbench for that module. It discusses the necessary components for the testbench, including a 'free running clock' declaration.

Objectives
After completing this training, student will be able to:

• Write code to create testbench.
• Instantiate UUT into testbench.
• Declare internal signals of testbench.
• Write process to apply stimulus within testbench.
• Discuss concurrent operations in the simulator.

Topics or Training Outline

Test-Bench Overview
Declaring components, signals
'Stimulus' process
Behavioral Modeling
Simulation Basics