VITAL v2.1i (VHDL)

Software & Version:
N/A

Audience
New to first year VHDL users, anyone interested in applying VHDL to the design process.

Prerequisites
Basic digital design, simulation and design verification concepts.

What is the level of the material?
Level II - Intermediate

Training Duration
1 Hour

Content Description
This 'VITAL' module discusses the IEEE 1076.4 standard and how it is applied within the Xilinx and simulation tool environment. It gives an overview of how timing is modeled in VHDL. It shows the structure and content of the .sdf and .vhd files. It also covers the underlying Xilinx library (SIMPRIM) files that must be present in order to use the VITAL capability.

Objectives
After completing this training, student will be able to:

• Discuss VITAL interface files (.sdf & .vhd).
• Select options in Xilinx P&R software to produce VITAL files.
• Apply delay data (.sdf) to the appropriate design region.
• Run simulation using VITAL in Model Tech or Aldec tools.
• Determine which Xilinx library VITAL support files must be compiled.

Topics or Training Outline

Delay Types
Delay Specification
SDF Files
Structural .vhd Files