Software & Version: 
1.5i Implementation tools (Alliance or Express)

Audience
Intermediate VHDL, Verilog, Xilinx design, and basic design. Customer could have completed one small slow design in VHDL or Verilog using Foundation or Alliance. Alternatively, students may have completed a class on VHDL or Verilog.

Prerequisites
Floorplanner I: Viewing Your Design

What is the level of the material?
Level III - Advanced 

Training Duration
1 hour

Content Description
Focuses on solutions to common layout problems experienced by designers of fast, large circuits. A fast circuit has a system clock frequency of 40 MHz.

Objectives
After completing this training, student will be able to:

• Layout pins to promote high speed and reduce ground bounce
• Improve timing delays and routability
• Create proper structured placement

Topics or Training Outline

Overview
Layout Tips for Input/Output Blocks
Layout Tips for Internal Logic
Known issues for version 1.5i 
Question/Summary

References