Introduction to Efficient Synthesis & Simulation (1.5i) 

Software & Version
Foundation v1.5i or Alliance v1.5i

Audience
New HDL designer who is new to Xilinx.

Prerequisites
Students need to have basic experience with VHDL or Verilog, such as completion of the Verilog CBT. It would be helpful but not required to have experience with HDL Editor.

What is the level of the material?
Level I  - Beginning

Training Duration
1 hour plus lab 

Content Description
This module focuses on general style guide, not functional elements. Both VHDL and Verilog are discussed.

Objectives
After completing this training, student will be able to:

• Easily Create efficient designs (moderate speed) with respect to the following topics:
  • RTL/Behavioral Code
  • Use VHDL Libraries correctly
  • Create a simple test bench 
  • Avoid code that does not produce similar/simulation results  

Topics or Training Outline

• Coding styles for moderate speed 
• Library use clauses
• RTL/Behavioral Code
• Create a simple test bench 
• Avoid code that causes pre and post simulation mismatches

References
As specified in HW Coding section: www.support.xilinx.com -> Xpert Journal, Xcell, App notes, On-line docs, VHDL and Verilog Reference Guide