Reading Reports (1.5i)     

Software & Version:
Foundation 1.5i or Alliance 1.5i

Audience:
New Xilinx user or anyone who has no experience reading Xilinx report files.

Prerequisites:
Completion of a simple FPGA design, either on-the-job or in another training module.

What is the level of the material? 
Level I - Beginning

Training Duration 
1 hour

Course Content Description: 
This module provides an overview of each report generated by the Xilinx Implementation Tools, and highlights the location of key information such as device utilization, maximum clock frequency, pinout, timing constraint information, logic trimming, etc.

Objectives: 
After completing this training, student will be able to:

• Describe the contents of each report generated by the Xilinx Implementation Tools 
• Select the correct report when looking for key design information  
• Locate key design information within the report 

Topics or Training Outline: 

• Overview of all reports 
• Translate Report 
• Map Report 
• Logic Level Timing Report 
• PAR Reports 
• Post-Route Timing Report 

References:
None