Software & Version
Foundation 1.5i or Alliance 1.5i 

Audience
Audience has no FPGA design experience. 

Prerequisites
Audience needs to understand basic FPGA architecture. 

What is the level of the material?
Level I   - Beginning 

Training Duration
1 hour 

Content Description
This training material focuses on placing basic timing constraints on an FPGA design using the Constraints Editor. 

Objectives
After completing this training, student will be able to:

• Apply basic timing constraints to a simple synchronous design.
• Specify basic timing requirements and pin assignments with the Constraints Editor.

Topics or Training Outline

Basic Timing Constraints
The value of Basic Timing Constraints
The Period and Offset Constraints
Pin Assignments
Pin Assignment guidelines
Making Pin Assignments in the Constraints Editor
Using the Constraints Editor for making Timing Constraints
Making a Period Constraint
Making an Offset Constraint

References
Refer to the M1 Constraints Guide on the DataSource CD (Development Systems Documentation M1 Documentation - M1 Constraints Guide. Refer to the Timing and Constraints Journal within the Expert Journals on the http://www.support.xilinx.com website.