Timing Constraints II Abstract

Timing Constraints II v1.5i

Software & Version:
Foundation 1.5I and Alliance 1.5i

Audience
Audience has no FPGA experience, but has completed the Timing Constraints I module.

Prerequisites
Audience needs to understand basic FPGA architecture and completed the Timing Constraints I module.

What is the level of the material?
Level II - Intermediate

Training Duration
1 hour

Content Description
This module focuses on placing path specific timing constraints on an FPGA design using the Constraints Editor. Applications such as grouping logic, constraining multi-clock domains, and grouping Offset In/Out constraints are covered.

Objectives
After completing this training, student will be able to:

Apply path specific timing constraints to specific design applications.
Specify path specific timing requirements with the Constraints Editor.

Topics or Training Outline

Introduction
Creating Groups
Creating Offset In/Out Groups
Inter-Clock Domain Constraining
Summary

References
Refer to the M1 Constraints Guide on the DataSource CD (Development Systems Documentation -> M1 Documentation -> M1 Constraints Guide). Refer to the Technical Tips on the http://www.support.xilinx.com website.