Essential VHDL and Synthesis for Xilinx FPGA Technology v1.5i

Cost:
$1000

Software & Version:
1.5i

Audience

Prerequisites
The attendee should have previous VHDL for synthesis experience or recent attendance at a VHDL course as well as knowledge of Xilinx FPGA Technology and Implementaion Tools software.

What is the level of the material?

Training Duration
2 Days

Content Description
This two-day course is designed to bridge the gap between having an understanding of VHDL for synthesis and specific programmable technology and learning how to write code, use specific synthesis and place & route tools to achieve the most efficient design. The hands-on exercises take engineers through the implementation of the most common and troublesome types of design problems, such as RAM, ROM, arithmetic functions, state machines, bi-directional asynchronous IO and repeated hierarchy. The attendee will learn how to obtain the best results with a choice of synthesis tools (Exemplar, Synplicity, or Synopsys).

Objectives
After completing this training, student will be able to:

• Identify which coding styles synthesize most easily into FPGA devices
• Describe how to access particular FPGA features through your VHDL code (clock buffers, power-on resets or macro functions)
• Identify a complete design flow
• Discuss the common errors that occur in the design flow and how to fix them

Topics or Training Outline

Day 1

• Course Introduction
• Xilinx Technology Overview
• Definition of RTL Code (RTE)
• Xilinx Design Flow Description
• Language Specific Optimizations
• Edge Filter Design
• Lab Exercises:
  • 8,000 gate Edge Filter design

Day 2

• Xilinx Technology Specific Optimizations
• Lab Exercises:
  • Implementation of each block of the Edge Filter design

References
None