Answers Database
Understanding the CPLD Fitter Report File
Record #2860
Product Family: Software
Product Line: EPLD Core
Problem Title:
Understanding the CPLD Fitter Report File
Problem Description:
Urgency: standard
General description:
How to read the CPLD Fitter Report File?
Solution 1:
This is a sample CPLD fitter report file. Clicking on the HyperLinks will take
you to the explanation of each term and symbol used.
SAMPLE CPLD FITTER REPORT
XACT: version M1.3.7 Xilinx Inc.
Fitter Report
Design Name: test
Fitting Status: Successful Date: 9-19-97, 5:56PM
**************************** Resource Summary ****************************
Design Device Macrocells Product Terms Pins
Name Used Used Used Used
test XC9572-7-PC84 8 /72 ( 11%) 15 /360 ( 4%) 61 /69 ( 88%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 48 48 | I/O : 56 7
Output : 5 5 | GCK/IO : 2 1
Bidirectional : 3 3 | GTS/IO : 2 0
GCK : 2 2 | GSR/IO : 1 0
GTS : 2 2 |
GSR : 1 1 |
---- ----
Total 61 61
GLOBAL RESOURCES:
Signal 'CLK1' mapped onto global clock net GCK1.
Signal 'CLK2' mapped onto global clock net GCK2.
Signal 'F1' mapped onto global output enable net GTS1.
The complement of 'T' mapped onto global output enable net GTS2.
Signal 'RESET' mapped onto global set/reset net GSR1.
POWER DATA:
There are 7 macrocells in high performance mode (MCHP).
There are 1 macrocells in low power mode (MCLP).
There are a total of 8 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
I1 1 2 FB1_2 STD FAST 1 I/O I/O
Y 1 2 FB1_6 STD FAST 3 I/O O
Y1 1 2 FB2_2 LOW FAST 69 I/O I/O
Y2 1 3 FB1_13 STD FAST 20 I/O O
Y3 1 4 FB3_10 STD FAST 40 I/O O
Y4 2 3 FB3_2 STD FAST 17 I/O O
Y5 1 3 FB2_10 STD FAST 75 I/O I/O
Y6 7 35 FB4_3 STD FAST 51 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
A1 FB1_10 13 I/O I
A2 FB2_17 84 I/O I
A3 FB4_6 54 I/O I
A4 FB2_13 80 I/O I
A5 FB4_1 46 I/O I
A6 FB3_7 35 I/O I
C FB4_13 61 I/O I
CLK1 FB1_9 9 GCK/I/O GCK
CLK2 FB1_11 10 GCK/I/O GCK
E FB1_7 11 I/O I
F FB3_6 34 I/O I
F1 FB2_7 76 GTS/I/O GTS
RESET FB2_9 74 GSR/I/O GSR
SET FB4_12 58 I/O I
START FB4_9 50 I/O I
T FB2_11 77 GTS/I/O GTS
X FB2_3 67 I/O I
X1 FB2_8 72 I/O I
X10 FB4_2 44 I/O I
X11 FB2_15 83 I/O I
X12 FB4_11 53 I/O I
X13 FB1_8 5 I/O I
X14 FB2_5 70 I/O I
X15 FB3_15 37 I/O I
X16 FB1_15 14 I/O I
X17 FB4_8 48 I/O I
X18 FB1_5 2 I/O I
X19 FB4_17 66 I/O I
X2 FB3_11 33 I/O I
X20 FB3_9 26 I/O I
X21 FB4_15 65 I/O I
X22 FB4_5 47 I/O I
X23 FB3_5 19 I/O I
X24 FB4_14 56 I/O I
X25 FB2_6 71 I/O I
X26 FB3_17 39 I/O I
X27 FB1_17 15 I/O I
X28 FB2_14 81 I/O I
X29 FB3_14 36 I/O I
X3 FB3_8 21 I/O I
X30 FB3_16 45 I/O I
X31 FB1_1 4 I/O I
X32 FB4_7 55 I/O I
X33 FB3_4 32 I/O I
X34 FB3_12 41 I/O I
X35 FB1_3 6 I/O I
X36 FB4_10 57 I/O I
X4 FB1_12 18 I/O I
X6 FB2_4 68 I/O I
X7 FB2_16 82 I/O I
X8 FB3_3 31 I/O I
X9 FB4_4 52 I/O I
Z FB3_13 43 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 3 6 7 3 2/1 18
FB2 2 5 5 2 0/2 17
FB3 2 6 7 3 2/0 17
FB4 1 35 35 7 1/0 17
---- ----- ----- -----
8 15 5/3 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 7
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 4 I/O I
I1 1 0 0 4 FB1_2 STD 1 I/O I/O
(unused) 0 0 0 5 FB1_3 6 I/O I
(unused) 0 0 0 5 FB1_4 7 I/O
(unused) 0 0 0 5 FB1_5 2 I/O I
Y 1 0 0 4 FB1_6 STD 3 I/O O
(unused) 0 0 0 5 FB1_7 11 I/O I
(unused) 0 0 0 5 FB1_8 5 I/O I
(unused) 0 0 0 5 FB1_9 9 GCK/I/O GCK
(unused) 0 0 0 5 FB1_10 13 I/O I
(unused) 0 0 0 5 FB1_11 10 GCK/I/O GCK
(unused) 0 0 0 5 FB1_12 18 I/O I
Y2 1 0 0 4 FB1_13 STD 20 I/O O
(unused) 0 0 0 5 FB1_14 12 GCK/I/O
(unused) 0 0 0 5 FB1_15 14 I/O I
(unused) 0 0 0 5 FB1_16 23 I/O
(unused) 0 0 0 5 FB1_17 15 I/O I
(unused) 0 0 0 5 FB1_18 24 I/O
Signals Used by Logic in Function Block
1: A1 4: START 7: Y5
2: A2 5: X 8: Z
3: D 6: Y1
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
I1 XX...................................... 2 2
Y ....X..X................................ 2 2
Y2 ..XX.@@................................. 3 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 5/31
Number of signals used by logic mapping into function block: 5
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 63 I/O
Y1 1 0 0 4 FB2_2 LOW 69 I/O I/O
(unused) 0 0 0 5 FB2_3 67 I/O I
(unused) 0 0 0 5 FB2_4 68 I/O I
(unused) 0 0 0 5 FB2_5 70 I/O I
(unused) 0 0 0 5 FB2_6 71 I/O I
(unused) 0 0 0 5 FB2_7 76 GTS/I/O GTS
(unused) 0 0 0 5 FB2_8 72 I/O I
(unused) 0 0 0 5 FB2_9 74 GSR/I/O GSR
Y5 1 0 0 4 FB2_10 STD 75 I/O I/O
(unused) 0 0 0 5 FB2_11 77 GTS/I/O GTS
(unused) 0 0 0 5 FB2_12 79 I/O
(unused) 0 0 0 5 FB2_13 80 I/O I
(unused) 0 0 0 5 FB2_14 81 I/O I
(unused) 0 0 0 5 FB2_15 83 I/O I
(unused) 0 0 0 5 FB2_16 82 I/O I
(unused) 0 0 0 5 FB2_17 84 I/O I
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: A3 3: A5 5: I1.PIN
2: A4 4: A6
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Y1 X...X................................... 2 2
Y5 .XXX.................................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 7
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 25 I/O
Y4 2 0 0 3 FB3_2 STD 17 I/O O
(unused) 0 0 0 5 FB3_3 31 I/O I
(unused) 0 0 0 5 FB3_4 32 I/O I
(unused) 0 0 0 5 FB3_5 19 I/O I
(unused) 0 0 0 5 FB3_6 34 I/O I
(unused) 0 0 0 5 FB3_7 35 I/O I
(unused) 0 0 0 5 FB3_8 21 I/O I
(unused) 0 0 0 5 FB3_9 26 I/O I
Y3 1 0 0 4 FB3_10 STD 40 I/O O
(unused) 0 0 0 5 FB3_11 33 I/O I
(unused) 0 0 0 5 FB3_12 41 I/O I
(unused) 0 0 0 5 FB3_13 43 I/O I
(unused) 0 0 0 5 FB3_14 36 I/O I
(unused) 0 0 0 5 FB3_15 37 I/O I
(unused) 0 0 0 5 FB3_16 45 I/O I
(unused) 0 0 0 5 FB3_17 39 I/O I
(unused) 0 0 0 5 FB3_18 (b)
Signals Used by Logic in Function Block
1: C 4: F 7: Y3.LFBK
2: D 5: SET 8: Y5
3: E 6: Y1
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Y4 ...XX.X................................. 3 3
Y3 XXX..@.@................................ 4 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 35/1
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 46 I/O I
(unused) 0 0 \/1 4 FB4_2 44 I/O I
Y6 7 2<- 0 0 FB4_3 STD 51 I/O O
(unused) 0 0 /\1 4 FB4_4 52 I/O I
(unused) 0 0 0 5 FB4_5 47 I/O I
(unused) 0 0 0 5 FB4_6 54 I/O I
(unused) 0 0 0 5 FB4_7 55 I/O I
(unused) 0 0 0 5 FB4_8 48 I/O I
(unused) 0 0 0 5 FB4_9 50 I/O I
(unused) 0 0 0 5 FB4_10 57 I/O I
(unused) 0 0 0 5 FB4_11 53 I/O I
(unused) 0 0 0 5 FB4_12 58 I/O I
(unused) 0 0 0 5 FB4_13 61 I/O I
(unused) 0 0 0 5 FB4_14 56 I/O I
(unused) 0 0 0 5 FB4_15 65 I/O I
(unused) 0 0 0 5 FB4_16 62 I/O
(unused) 0 0 0 5 FB4_17 66 I/O I
(unused) 0 0 0 5 FB4_18 (b)
Signals Used by Logic in Function Block
1: X1 13: X20 25: X31
2: X10 14: X21 26: X32
3: X11 15: X22 27: X33
4: X12 16: X23 28: X34
5: X13 17: X24 29: X35
6: X14 18: X25 30: X36
7: X15 19: X26 31: X4
8: X16 20: X27 32: X6
9: X17 21: X28 33: X7
10: X18 22: X29 34: X8
11: X19 23: X3 35: X9
12: X2 24: X30
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Y6 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX..... 35 35
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
/I1 = /A1 */A2
I1.TRST= F1 ;FOE/GTS
Y1 = A3 * I1.PIN
Y5 = A4 * A5 */A6
Y = X * Z
Y.TRST = /T ;FOE/GTS
/Y2 = /START */D
Y3 := C * E * D
Y3.CLKF = CLK2 ;FCLK/GCK
Y3.PRLD = GND
/Y4 := /F */Y3.LFBK
Y4.CLKF = CLK1 ;FCLK/GCK
Y4.SETF = SET
Y4.RSTF = RESET ;GSR
Y4.PRLD = GND
Y6 = X1 * X2 * X3 * X4
+ X4 * X6 * X7 * X8 * X9
+ X17 * X18 * X19 * X20 * X21
+ X22 * X23 * X24 * X25 * X26
+ X27 * X28 * X29 * X30 * X31
;Imported pterms
+ X32 * X33 * X34 * X35 * X36
;Imported pterms
+ X10 * X11 * X12 * X13 * X14 * X15 * X16
D = Y1 * Y5 ; FC node
**************************** Device Pin Out ****************************
Device : XC9572-7-PC84
C C
L L G T X X X X X X T V
K K N I 3 1 3 1 I A 1 X 2 A I C F Y
E 2 1 D E 5 3 1 Y 8 1 2 1 7 8 4 E C T 1 5
--------------------------------------------------------------
/11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \
TIE | 12 74 | RESET
A1 | 13 73 | VCC
X16 | 14 72 | X1
X27 | 15 71 | X25
GND | 16 70 | X14
Y4 | 17 69 | Y1
X4 | 18 68 | X6
X23 | 19 67 | X
Y2 | 20 66 | X19
X3 | 21 XC9572-7-PC84 65 | X21
VCC | 22 64 | VCC
TIE | 23 63 | TIE
TIE | 24 62 | TIE
TIE | 25 61 | C
X20 | 26 60 | GND
GND | 27 59 | TDO
TDI | 28 58 | SET
TMS | 29 57 | X36
TCK | 30 56 | X24
X8 | 31 55 | X32
X33 | 32 54 | A3
\ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
--------------------------------------------------------------
X F A X X V X Y X G Z X X A X X G S Y X X
2 6 2 1 C 2 3 3 N 1 3 5 2 1 N T 6 9 1
9 5 C 6 4 D 0 0 2 7 D A 2
R
T
Legend : TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : 95*
Use Timing Constraints : ON
Ignore Assignments In Design File : OFF
Create Programmable Ground Pins : OFF
Use Advanced Fitting : OFF
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Use Global Nets : ON
Collapsing pterm limit : 15
Collapsing input limit : 36
Glossary of Terms
Resource Summary
A listing of Used and Unused Device Resources after Fitting.
Power Data
Macrocell Power usage data to be used in conjunction with the following equation:
ICC(mA) = MCHP(1.7) + MCLP(0.9) + MC(0.006 mA/MHz)f
Where:
MCHP = Macrocells in high-performace mode
MCLP = Macrocells in low-performance mode
MC = Total number of Macrocells used
f = Clock frequency (MHz)
Resources Used by Successfully Mapped Logic
LOGIC - A list of the Physical Locations, Slew Rate, Power modes, Number and
Type of Signals used by the mapped logic.
INPUTS - A list of all User Inputs with their Physical Locations and Types.
Imported & Exported Product Terms
The \/ sign shows that Pterms are being exported to the next adjacent macrocell below and the /\
sign shows that Pterms are being exported to the next adjacent macrocell above. The <- sign
indicates the Local macrocell using imported Pterms. In this particular example, the signal Y6
uses a total of 7 Pterms; 5 local, 1 Pterm from the macrocell above it and 1 Pterm from the
macrocell below it.
Legend
Signal Name - Macrocell output signal name
Signals Used - Number of signals used in the Product Terms. See Note 1.
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
FBx_y - Logic has been mapped in Function Block x, Macrocell y
FB Inputs Used - Used Function Block Inputs
O/IO Req - Required number of Outputs and I/Os for that particular Function Block
IO Avail - Available I/O in that particular Function Block
X - Signal used as an input to Macrocell logic
@ - Signal used a wire-AND input to Macrocell logic. See Note 2.
Pwr Mode - Macrocell power mode
Slew Rate - Slew Rate of the output pad
Pin # - Actual Package Pin number
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
I/O - Bidirectional GSR - Global Set/Reset
(b) - Buried(unbonded) macrocell
Equation Syntax
.TRST - The 3state/output enable control signal. This could be a Pterm or a global line
.CLKF - The Clock source driving the Flip-Flop. This could be a Pterm or a global line
.RSTF - Signal Driving the Clear pin of the Flip-Flop. This could be a Pterm or a global line.
.SETF - Signal Driving the Preset pin of the Flip-Flop. This could be a Pterm or a global line.
.PRLD - Defines the Power of State of the Flip-Flop. It could be PRESET(VCC) or CLEARED(GND)
.PIN - Signal on the LHS of the equation is driven by signal on the RHS using pin feedback
.LFBK - Signal on the LHS of the equation is driven by the signal on the RHS using Local
Macrocell feedback
FC Node - Signals forming a Wire-AND in the switch matrix.
TIE - Tie pin to GND or board trace driven to valid logic level
VCC - Dedicated Power Pin
GND - Dedicated Ground Pin
TDI - Test Data In, JTAG pin
TDO - Test Data Out, JTAG pin
TCK - Test Clock, JTAG pin
TMS - Test Mode Select, JTAG pin
Compiler Options
The CPLD fitter uses all the compile options shown in the list. The user can
turn these options ON or OFF from the XC9500 templates in the Xilinx Design
Manager.
Note 1
In the CPLD architecture, every I/O block is connected to its specific macrocell. So, an I/O pin
connected to macrocell FBx_y can only be driven by that macrocell. However, if the I/O pin
is not being driven by macrocell FBx_y (a buried macrocell), then it can be used as an input
pin by some other User Input signal. This may lead to some confusion, if the user looks in the
"FB*" section of the report. For a particular Macrocell output signal name, the user may see the
Pin connected to that macrocell as being used as an Input even if that particular signal is not
a User Input signal. This can be cleared up by looking in the INPUTS subsection of the
"Resources Used by Successfully Mapped Logic" section of the report. The physical location of the
User Input along with the signal name is reported in this section.
Note 2
The reported number of Signals Used as inputs to Macrocell logic may exceed the number of
FB Inputs Used (36) due to the fact that the signals used to create a wire-AND (in the switch
matrix) that drives the macrocell show up as well. The Number of signal used in a Function Block
is equal to the sum of Xs and @s.
End of Record #2860 - Last Modified: 12/08/99 10:52 |
