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Xilinx Design Reuse FAQ

Q: Why is Xilinx launching an Internet design reuse initiative for programmable logic?
A: In October 1998, Xilinx announced the Virtex series, the world's first FPGA family to offer one million system gates. In September of 1999, Xilinx announced the Virtex-E series, which offers FPGAs with up to three million system gates. The rapid market acceptance of these very large programmable logic devices by traditional ASIC designers is driving the Xilinx reuse initiative. In the past, designers have turned to programmable logic because it offers tremendous flexibility and time-to-market advantages over gate array or standard cell technologies. As FPGAs become ever larger, one way to help retain this time-to-market advantage is through the reuse of intellectual property developed by customers for earlier designs. The Xilinx design reuse initiative will benefit programmable logic customers who develop their own IP, and it will benefit third-party IP developers in the Xilinx AllianceCORE program. The Internet component continues the Xilinx Silicon Xpresso initiative which the company announced in the fall of 1998 to step up use of the Internet to help increase the productivity of designers who use programmable logic.

Q: What does the Xilinx design reuse initiative involve?
A: The intent of the initiative is help customers implement designs for reuse and share their intellectual property internally. The first offerings include the IP Internet Capture and IP Internet Interface tools and an FPGA design reuse manual. The IP Internet Capture tool allows customers to easily capture and package intellectual property they have already created for Xilinx FPGAs and share it inside their company with other design teams over the Internet. The IP Internet Interface tool provides customers and third-party developers a method to integrate their own parameter-driven IP with the Xilinx CORE Generator system. These designs can be distributed or sold over the web in a secure environment. As part of the initiative, Xilinx also announced the publication of the "ASIC Designers Programmable Logic Reuse Manual," a supplement to the "Reuse Methodology Manual" from Synopsys and Mentor Graphics. The Xilinx reuse manual provides guidelines for designers who want a common strategy for reusing intellectual property, regardless of whether it was developed for ASICs or for FPGAs.

Q: How do IP developers get these new design reuse tools?
A: All the design reuse tools will be available from the Xilinx IP Center at www.xilinx.com. Xilinx has set up a new area on the Xilinx IP Center where IP developers can register find the latest documents and tools. The IP Internet Capture and IP Remote Interface tools will be available in December 1999 from the Design Reuse area of the Xilinx IP Center at www.xilinx.com.

Q: What is the price of the tools?
A: The new IP Capture and the IP Remote Interface tools are available free of charge, as is "Xilinx Design Reuse Methodology for ASIC and FPGA Designers."

Q: How does the Xilinx design reuse initiative help ASIC designers?
A: Xilinx believes that customers who make design reuse part of their product planning strategy can gain time-to-market advantages and a competitive advantage. Companies can also preserve prior investments in engineering time spent in the creation of intellectual property. By reusing previously created modules of FPGA logic, a design team will not have to design similar modules again from scratch. But for this to happen, companies will have to change their culture and internal processes to facilitate the proper design and documentation of modules of intellectual property that ultimately will be targeted for reuse. Such reusable design modules can save critical time in getting new products to market. A goal of the Xilinx design reuse initiative is to help customers create a structure to catalog their current internal IP. By using tools such as the Xilinx IP Internet Capture tool, design teams will be aware of all the IP available in their company for Xilinx FPGAs. Many companies redesign modules simply because design teams do not communicate or catalog what they have done. The Xilinx IP Internet Capture tool bridges the communication gap between design teams and promotes effective communication among design teams so that IP can be reused again and again. It does this by providing a methodology for individual engineers to send their designs to a corporate design reuse catalog.

Q: How will the Xilinx reuse manual help ASIC designers?
A: The new "Xilinx Design Reuse Methodology for ASIC and FPGA Designers" is intended for designers who need to be able to target both ASIC and FPGA architectures with the same RTL code. The Xilinx supplement to the Synopsys and Mentor Graphics "Reuse Methodology Manual" provides an overview of FPGA system level features and contains general RTL synthesis coding guidelines that have the most impact on improving system performance. About half of the design reuse issues covered in the "ASIC Designers Programmable Logic Reuse Manual" are targeted at "best coding practices." This means that while the particular coding technique will optimize the use of logic resources and the performance in an FPGA, it will also do the same for an ASIC design. By enforcing corporate coding and documentation standards, a company will greatly improve the quality of the HDL modules that they are targeting for reuse.

Q: Why should an ASIC designer write code that can target an FPGA?
A: With the density of the Xilinx Virtex-E devices expected to exceed 3 million gates in 2000, FPGAs are becoming a more attractive alternative for designs that were typically targeted at ASICs. With more and more IP available from both internal and external sources, companies now have the option to use FPGAs for large, performance-driven designs. IP can be used in a modular design environment in the same way that cell based designs are done today. When ASIC designers code their HDL to be FPGA "friendly," they gain more options in the ever-increasing pressure to beat the competition to market. While a particular coding technique will optimize the use of logic resources and the performance in an FPGA, it can also do the same for an ASIC design. Many of the guidelines in the Xilinx reuse manual for programmable logic are simply good design practices and will enhance IP reuse and performance. Some of the concepts that target FPGAs include documentation, implementation, verification and coding strategies. The FPGA design reuse methodology can be used to enable IP creation and delivery in either an FPGA or ASIC context. This will enable customers to incorporate IP infrastructures for ASICs and FPGAs, including high-speed techniques that take advantage of Virtex system level features. Conceptually, this means that targeting an FPGA implementation will be a straightforward as selecting a different technology library for ASIC synthesis.

Q: How will the Xilinx IP Internet Capture tool help designers share IP?
A: Some programmable logic users report that with so many teams working on FPGA designs, it's difficult to keep track of what IP has been created within a company, what IP has been developed by their own team, what IP needs to be designed. To solve this, the IP Internet Capture tool operates with the cataloging capability of Xilinx CORE Generator system. The IP Internet Capture tool makes design modules created by individual engineers available to others who are using the Xilinx CORE Generator. Q: How does the Xilinx IP Internet Capture tool help address the need to document of IP for FPGAs? A: The Xilinx IP Internet Capture tool requires designers to provide links to documentation. This ensures that all the IP cataloged in the Xilinx CORE Generator system provides a useful starting point for engineers to evaluate whether the IP will meet their reuse needs.

Q: Why have companies found it hard to implement a design reuse infrastructure?
A: Even though the EDA industry has been addressing the issue of design reuse for several years, it's still a new area for many companies. In some engineering organizations, for example, it's all but impossible for design teams to find out what internal IP already is at their disposal. In others, there is a fundamental distrust of any intellectual property "not invented here" -- whether that IP is from a third party or from another team in the same organization. Still other groups don't want to make the initial effort. The challenge for those who manage design efforts will be to understand both the good news and bad news about design reuse. The bad news is that learning how to design for reuse initially will cost engineering time and may cut into schedules. But the good news that this investment in time ultimately will shorten the time required to do subsequent designs.

Q: Why would IP developers in the Xilinx AllianceCORE program use the IP Remote Interface tool?
A: With the Xilinx IP Remote Interface, IP providers have the option to create and package parameterizable cores. This interface allows an IP provider to create a custom GUI and executable that can be designed to collect the information needed to create a core. The information collected in the GUI is passed to an executable which can select from a set of fixed functions, HDL source code with generics, or simply write a structural netlist. These cores are then accessible to the customer through the Xilinx CORE Generator system

Q: Why would IP providers use the Xilinx CORE Generator system's IP Remote Interface feature to point to a set of fixed netlists?
A: By designing a GUI that uses the customer input parameters to simply select a fixed netlist, the IP provider can guarantee that the solution delivered to the customer is from a qualified, limited set. This allows the IP provider to fully test and verify the selected solutions. The IP provider has the flexibility to deliver to customers, through the Xilinx CORE Generator system, a core that has a number of solutions, but in a controlled, supportable, and secure method.

Q: How does the IP Remote Interface feature provide IP security for fixed netlists?
A: When IP providers deliver a single, fixed core from a set of fixed cores, they can also apply a Xilinx encryption algorithm to it. The Xilinx tools can read this file, but will protect the content from being viewed or exported in clear text. The Xilinx Foundation Series simulator can perform secure functional and timing simulation using these secure encrypted netlist cores. Alliance series too?

Q: How can the IP Remote Interface feature be used to modify synthesizable HDL code?
A: An IP provider can create a GUI that collects the input variables, which are then used to modify generic variables in VHDL or Verilog source code. This source code can be synthesizable behavioral or structural code. This source code is modified and then deposited in to the customer's project directory by the Xilinx CORE Generator system. The customer would instantiate this core just like any other hierarchical modules they may have.

Q: How can the IP Remote Interface feature be used to execute algorithmic code?
A: IP providers can use the IP Remote Interface to parameterize and run their algorithmic code that writes as an output file a supported netlist. They can develop algorithms that can write VHDL, Verilog, EDIF or even C++.

Q: Why would an IP provider use the IP Remote Interface feature to access sites on the Internet?
A: One of the powerful features of the IP Remote Interface is that it can be used to create cores which, when installed in the CORE Generator's IP tree, can launch applications that access files and programs on the Internet. IP providers can use this feature to control access to their source files. Having the ability to update and patch any of their cores allows IP providers to provide their customers with the latest and most up-to-date cores. Not only does this keep the customers current, it makes supporting the cores easier.

Q: How does the IP Remote Interface feature provide IP security over the Internet?
A: The IP Remote Interface allows IP providers to leverage the Internet's capability to securely authenticate customers. This security can be used to control access. It can also be used to collect payments using E-commerce. In one scenario, IP providers could authenticate a customer with a password, charge the customer account using E-commerce, gather the customer's input parameters through a web GUI, modify behavioral HDL source code, run a synthesizer on their server, write the EDIF netlist, call the Xilinx encryption API, and post back to the customer a secure encrypted netlist and compiled behavioral model.

Comments, Questions, Problems, Please E-mail DesignReuse@xilinx.com