FAQ - Partial Reconfiguration

Q. What is dynamic reconfiguration? 
A.  Dynamic reconfiguration is the ability to update only a portion of the configuration memory in a FPGA with a new configuration without stopping the functionality of unchanged sections of the FPGA. 

Q. Can the Virtex series of FPGAs support dynamic reconfiguration? 
A  Yes, except for the Block SelectRAMs.

The configuration logic is separate from the user logic and does not require use of normal resources allowing for continued operation of sections that do not change. The configuration write sequence is a glitchless operation, so that only the memory bits that were modified are toggled.

The one exception to this is the Block SelectRAM. Implementing a third read/write port for the RAM cells specifically for configuration would have been too costly in terms of area and RAM performance. The configuration logic requires the use of the read/write ports of the Block SelectRAMs when the memory contents must be read or written.

Q. What is the smallest portion that can be changed at one time? 
A. The smallest amount of configuration memory that can be written to or read from is a frame. A frame spans from the bottom of the device to the top of device, including the IOBs and CLBs, and contains a section of the data needed for each row.

There are 48 frames per CLB column. Frame size is dependent of the device size and ranges from 384 bits for a XCV50 to 1248 bits for a XCV1000.

Q. If so, what is the granularity of change? 
A. While an entire frame must be written into the device, only the bits that have changed will be toggled. This can allow a single bit to be changed without affecting the rest of the device operation.

Q. Can the routing be changed in a similar manner? 
A. The routing configuration memory is modified in the same manner as the logic configuration. Contention can occur during modification of routing connectivity, this is not recommended.

For designs that require changing large modules across multiple columns, the short term contention (<30mS) for this operation will not damage a Virtex device.

Q. If a signal passes through a section of change, will it continue to pass the data during the reconfiguration? 
A. Yes, providing that the reconfiguration does not intentionally change connections to the signal wire.

Q. What happens to the clock during reconfiguration?
A. The clock continues to operate as normal.

Q. Is the clock in the remainder of the chip affected by reconfiguration of another section? 
A. No. The global clock network is highly buffered and load independent, so no performance difference will be noticed. 

Q. Is the locking of the DLL affected by the dynamic connection and disconnection of logic in the device? 
A. Not unless the clock feedback path is reconfigured. Adding or removing loads from the clock network will have no noticeable affect on the global clock network delay. 

Q. Is it possible to reconfigure more than one column at a time using some form of
wildcards? 
A. If the frames to be configured are addressed sequentially, then the frame addresses may be auto-incremented. 

Q. How many configuration ports are supported?
A. For partial reconfiguration only the SelectMAP (8-bit) and JTAG (1-bit) ports can be used.

Q. What are the SelectMap and JTAG interface specifications for partial reconfiguration? 
A. These port specifications can be found in the Virtex DataSheet and have the same connectivity and timing parameters as full configuration. 

Q. What tool support will be provided to assist with dynamic reconfiguration?
A. Because partial reconfiguration can take on many different forms, there are no specific tools that are currently in development. Xilinx is working on feature enhancements to be included in future versions of the Xilinx implementation software to improve routing and placement of design modules.

Xilinx application notes relating to partial reconfiguration, when appropriate, will contain tactical software demonstrating how to create partial reconfiguration and readback bitstreams. The first application note to contain software of this nature is XAPP153 "Status and Control Semaphore Registers Using Partial Reconfiguration".

Q. If tools were not planned, would Xilinx be prepared to release details of the Virtex
configuration memory map and file structures so that we could consider writing our own
tools? 
A. Xilinx has released a significant amount of details of the Virtex configuration bitstream in XAPP151, "Virtex Configuration Architecture Advanced Users' Guide." The details presented in this application note provide the necessary information for designers to create and manipulate certain parts of the bitstream.

There are no plans to release information providing detailed information on the routing, CLB or IOB configuration, because to do so would compromise customer design security. In addition, any design that was hand-crafted through bitstream manipulation of routing and CLB configuration would not have DRC or timing analysis available for it, leading to unstable designs.

Q. Does Xilinx believe that dynamic reconfiguration has a commercial future? 
A. Yes. Dynamic reconfiguration of FPGAs can allow for more features to be enabled in end-user designs. This is similar in the manner with computers with large hard drives storing applications for days and months before the are needed. In a similar manner, particular logic functions may be stored in memory until the need arise for them to be configured into an FPGA.

Q. Does Xilinx intend to include more of the features of the XC6200 family in future
generations of Virtex? 
A. Future generations of Virtex will improve upon the current capabilities of Virtex. These improvements may incorporate some aspects of the XC6200 family.

Q. How much configuration data needs to be sent to the device to make the smallest
possible change? 
A. This varies with the frame size, it requires 384 bits + 1 frame + 1 dummy frame for a write operation. For a XCV300 this would be 1784 bits for a single frame write.

Q. What is the fastest time in which a change can be performed? 
A. Using the previous example and the SelectMAP port at 50MHz it would require 1784/8*20ns =4.32uS.

Q. When changing logic, what happens to the current contents of a flip-flop?
A. The state of the flip-flop remains the same unless GSR is asserted.

Q. When making a change, what happens to the current contents of a RAM?
A. If the frame contains RAM bits, the RAM will be updated with the new bits included in the frame.

Q. If a complete section of logic is replace containing multiple flip-flops, is there any
automatic form of local reset? 
A. No, a local user reset net should be used for this function.

Q. Can the contents of a register be modified via the configuration port and its status read? 
A. The contents of a register can not be modified from the configuration logic. The state of a register can be read in conjunction with the CAPTURE_VIRTEX special block to first capture the state of the register. XAPP153 shows a way of creating status and control registers using LUTs instead of registers.

Q. Can the configuration process be synchronized to the logical clock, or is it
asynchronous? 
A. The configuration process can not be synchronized to a logical clock.

Q. Is there any form of configuration buffer, or does all configuration 'trickle' into place? 
A. The configuration data is buffered at several different stages in the Virtex devices. The largest buffer is the frame buffer, with the entire contents of the frame written into the frame memory cells at the same time.

Q. What level of contention on signals can be tolerated during configuration? 
A.While reconfiguring routing across several columns the amount of contention current for this short amount of time will not be significant enough to damage a Virtex device. The reconfiguration time should be limited to <30mS reduce current consumption and possible damage. 

Q. Will information be provided in order to deduce the functionality associated with every single bit of a bitstream? 
A. There are no plans to release full documentation on the bitstream as it would compromise customer design security. 

Q. If not, which aspects of the bitsream will be open and which will be withheld? 
A. Xilinx has provided information on accessing the LUT contents, register state capture bits and the configuration contents in XAPP151. A future version of this application will also provide information on the Block SelectRAM contents. No further information disclosure is planned.

Q. Are features such as JTAG disabled during a partial reconfiguration process? 
A. No features are disabled during a partial reconfiguration.

Q. Can I/O cells be reconfigured independently of the internal logic? 
A. The I/O cells on the left and right edges of the device reside in separate columns from the CLB logic. The I/O cells on the the top and bottom edges of the device are included in the same frames as the CLB logic.

Q. Can I/O cells be reconfigured in a way that ensures that the status of the pin is always under control? 
A. In the same manner as the CLB logic, if the I/O cell configuration is not changed the reconfiguration write operation will not cause the memory bits to toggle.

Q. What would be the effect of adjusting the CLKDLL configuration bits during operation to adjust clock division ratio? 
A. This could potentially generate an extra clock edge or suppress an edge depending on the previous state of the CLKDV_DIVIDE value.

Q. What is the effect of leaving a section of routing of any length un-driven? 
A. Unused routing in Virtex is held at at logic 1 level by design.

Q. Is there any form of error checking (CRC) performed by the device during partial
reconfiguration? 
A. This option is left to the designer to decided to include in the bitstream. Further details are available in XAP151.

Q. If so, how will an error be indicated, and what will happen to the device?
A. If a CRC error is detected it will be flagged in the configuration status register only and the part will continue to operate.