1.0. Introduction

Thank you for purchasing the Reed-Solomon Decoder LogiCORE from Xilinx! The Xilinx Reed-Solomon Decoder LogiCORE provides you with a high performance, low cost, pre-implemented design, optimized for Xilinx FPGA's. This can save you many months of engineering time. 

This release note supports Version 1.0.0 of the Reed-Solomon Decoder LogiCORE. The following device families are supported in this release: 

1.1. Contents

The contents of the Reed-Solomon Decoder LogiCORE are listed in the following sections. All customers are entitled to download the design files using the web based configuration and download tool.

1.2. Software

The full set of deliverable files from the web based configuration and download tool is described below. 

*.edn

This is the netlist for the Reed-Solomon Decoder Core, elaborated with your required parameters. The netlist name corresponds to the component name you selected in the GUI.

You may rename this netlist file, however it must be identical to the instance name of the entity in the design that instantiates it.

rsdec_wrap.vhd

This is an example VHDL design to illustrate how to instance the Core. The entity name for the RS decoder can be whatever you like but you must ensure the netlist for the Core has the same name.

It is assumed that a synthesis tool will take care of adding ipads and ibufs to the primary inputs and obufs and opads to the primary outputs. The 'reset' signal should be driven onto the GSR (Global Set Reset) net. Most synthesis tools have a command to allow this to be specified. If not, it can be done explicitly by instancing a STARTUP component. This is explained in the Xilinx implementation tools documentation.

The 'clk' input should be driven by a global clock buffer. Again, synthesis tools usually have a command to specify this. If not, it can be done explicitly by instantiating a BUFG component. This is explained in the Xilinx implementation tools documentation.

The comments within the file explain how to instantiate a behavioral model for simulation, instead of a black-box component for synthesis. Another option is to instantiate a netlist, back-annotated from the Xilinx tools. The necessary modifications are also explained in the comments within the file.

rsdec_wrap.v

This is a Verilog version of rsdec_wrap.vhd.

rs_decoder.vhd

This is a VHDL behavioral model. The rsdec_wrap.vhd file shows how to instantiate this model. Note that the model only behaves correctly if the inputs do not violate any of the rules described in the core data sheet.

This model contains no timing information. The advantage in using the behavioral model is that simulation run times are considerably reduced compared with using a back-annotated netlist model.

Limitations:

1. No timing information.
2. Likely to react to unknown or 'X' inputs differently to the structural model.
3. Likely to react differently to out-of-specification inputs. i.e. input control signal behavior that does not follow the rules defined in the data sheet.
4. After an asynchronous reset, the behavioral model will output zeroes on 'data_out' until the latency has elapsed. After this time, the values sampled on 'data_in' after the reset will start to appear on 'data_out'. The real circuit behaves slightly differently. After an asynchronous reset, the values appearing on 'data_out' are undefined until the latency has elapsed.

A back-annotated netlist model can be used to get round these limitations during simulation.

rs_decoder.v

This is a Verilog version of rs_decoder.vhd.

dec_spec.pdf

This is the current version of the Core data sheet.

1.3. Maintenance

This product comes with one year of maintenance from the original purchase date; you are entitled to receive major product and documentation updates during that time. 

1.4. Support

This product comes with free technical and product information telephone support (toll free in the U.S. and Canada). You can also fax or email your questions. 

The fastest method for obtaining technical support is through the http://www.support.xilinx.com/support/techsup/tappinfo.htm web page. Your inquiry is routed to a team of engineers with specific expertise in using the Reed-Solomon Decoder LogiCORE. 

Xilinx provides technical support for usage of the Reed-Solomon Decoder LogiCORE product as described in the Xilinx Reed-Solomon Decoder LogiCORE datasheet. Xilinx does not guarantee functionality or support of the Reed-Solomon Decoder LogiCORE product if designs are not implemented in supported devices or it is utilized in a manner other than described in the Xilinx Reed-Solomon Decoder LogiCORE datasheet.

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2.0. Installation

This section explains the system requirements and how to install the Reed-Solomon Decoder LogiCORE after downloading it from the web based configuration and download tool. 

2.1. System Requirements

In order to use the Reed-Solomon Decoder LogiCORE, you must verify that your computing platform is capable of running the required design tools. Consult the documentation shipped with your design tools to verify that your computing platform is sufficient. 

The Xilinx Reed-Solomon Decoder LogiCORE requires the use of either Xilinx Alliance M2.1i (or later) or Xilinx Foundation M2.1i (or later).  The Reed-Solomon Decoder LogiCORE has been verified with a large number of parameter combinations in all the supported device families.

The supplied behavioral models have been verified with

• Model Technology ModelSim PE v5.2e

The size of the emailed design file (zip or tar) varies depending on the parameters selected. It is typically less than 1 MByte but it could be greater. Please ensure you have suffient capacity in your email buffer to receive the file. 

2.2. Unpacking Files

During configuration and download, a selection is made between ZIP format and GZ format for the download. The contents of the ZIP file and the GZ file are identical. 

If you have downloaded the ZIP file, then you can use any unzip utility to decompress and extract the files.  Suitable tools include "unzip" on UNIX workstations, and "winzip" on Microsoft Windows platforms. 

If you have downloaded the GZ file, you must first decompress the file using the GNU "gunzip" utility.  After decompressing the file, extract the files from the TAR archive using the command "tar xvf filename.tar".  These utilities are readily available on UNIX workstations. For ease of use, users of Microsoft Windows should download the ZIP file instead of the GZ format file. 

Make a cursory comparison of the resulting files to the list presented in the Software section to make sure you received all the files. 

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3.0. Known Issues

This is a list of known issues. Please read this entire section so that you are aware of any late breaking information. 

3.1. Functional Simulation

None. 

3.2. Synthesis

None. 

3.3. Implementation

Various warnings may be issued by the Xilinx tools. However, no errors should occur.  

3.4. Timing Simulation

None. 

3.5. Documentation

None. 

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4.0. Customer Support

For registration, authorization codes, update information, warranty status, shipping, product issues, and technical support, call Monday through Friday, 8 a.m. to 5 p.m. Pacific time. 

4.1. Registration

You must be a registered customer to access the web based configuration and download tool. If you have questions regarding your registration status, or forget your password, you may contact Xilinx Customer Service for assistance: 
 

United States and Canada	1-800-624-4782
International	Contact your local distributor

4.2. Technical Support

Technical support may be reached via the following web page: 
http://www.support.xilinx.com/support/techsup/tappinfo.htm

4.3. Training

The Xilinx Training Administrator may be contacted at 1-408-879-5090. International customers should contact a local sales representative or distributor. 

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