Essential VHDL and Synthesis for Xilinx FPGA Technology  

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Course Dates:  May 11-12 and July 20-21 

Overview:  
The training course is designed to bridge the gap between having an understanding of VHDL for synthesis and specific programmable technology and learning how to write code, to use specific synthesis and place & route tools to achieve the most efficient design. 

 The hands-on exercise takes engineers through the implementation of the most common and troublesome types of design problems, such as RAM, ROM, arithmetic functions, state machines, bi-directional asynchronous IO and repeated hierarchy to name but a few. These features are all integrated into a single, complete design application which we have specifically created to show the efficient use of VHDL on a real project. 

Since different synthesis tools have different capabilities, the workshop will teach how to obtain the best results with your choice of synthesis tool from either Exemplar, Synplicity or 
Synopsys. 

The Workshop is Designed for: 
     Engineers who will be using VHDL to target a Xilinx FPGA device 

The Main Topics Covered: 

• Short overview of Xilinx FPGA device architecture 
• Coding styles which synthesize most easily into FPGA devices 
• How to access particular FPGA features through your VHDL code, for example clock buffers, power-on resets or macro functions 
• Detailed look at the complete design flow 
• Discussion of the common errors that occur in the design flow and how to fix them 
• How to design state machines which will give the best implementation results 
• Hands-on exercise to develop the most generic VHDL description of our design and take it through the complete design flow 
• Hands-on exercise to modify the VHDL code to give the fastest and then the smallest implementations and take them through the complete design flow 

Course Outline: 

• Xilinx Workshop Introduction: course objectives, conventions used, overview of agenda. 
• Xilinx Technology Overview: an overview of the Xilinx FPGA architecture and features. 
• Definition of RTL Code (RTE): a reminder of the RTL coding style, and some of the main issues in writing code which is portable between different synthesis tools.
• Xilinx Design Flow Description: a detailed look at the design flow for the simulation, synthesis and implementation of a Xilinx design. 
• Language Specific Optimizations: an in-depth look at VHDL coding techniques for effective targeting of programmable logic architectures. 
• Edge Filter Design: an overview of the lab sessions and an introduction to the Edge Filter design upon which the labs are based. 
• Lab Exercises: The lab exercises on day 1 are designed to familiarize students with taking the 8,000 gate Edge Filter design through the complete design flow using their chosen set of simulation and synthesis tools. 

• Xilinx Technology Specific Optimizations: detailed look at the optimization techniques for targeting Xilinx technology and architecture including the pros and cons of using technology specific cells. 
• Lab Exercises: The lab exercises on day 2 take most of the day, and involve optimizing the implementation of each block of the Edge Filter design to achieve the smallest and fastest implementations. 

 

Registration: 
To attend this course, please call 877-XLX-CLASS (877-959-2527) to register. Please reference Customer Education code EVHDL when registering.