Device Replacement Guide - XC4000A Family

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Purpose

This Device Replacement Guide is designed to help customers who are in production with a Xilinx FPGA that is planned to be made obsolete. General guidelines are given for how to convert an existing XC4000A design to an alternative Xilinx FPGA device. This guide details devices that are pinout compatible with the XC4000A device and outlines the main differences that must be considered when converting a design.

Reason for Discontinuance

The performance/cost gains achieved with the recently introduced XC4000E family, which uses an advanced three-layer metal process, have meant that the substantial cost advantage that the XC4000A family offered over the XC4000 does not apply to the XC4000E. By making the XC4000A family obsolete, Xilinx can focus design and support efforts on a smaller number of devices and to achieve a better cost structure for the XC4000E devices. For designs without RAM, the XC5200 family may offer an even more cost-effective solution.

Timeline

Conversion Guidelines and Considerations

The devices listed in Table 1 below are pin-for-pin replacements for designated XC4000A devices. They are not, however, bitstream compatible. Designs must therefore be recompiled through the XACT ^(R) tools.

Replacement Devices will be equivalent or lower priced than current devices in all cases.

If converting to an XC4000E device, schematic changes will probably not be necessary. With a couple of minor exceptions, XC4000E devices have all of the same features as XC4000A devices (see Table 2). An exception is if the 24 mA drive capability of the XC4000A is used in the design. In this case, output pins may need to be paired in order to sink the required output current. This will affect the board design. Another exception is the more flexible output slew rate in the XC4000A. Outputs designated as Medium Fast or Medium Slow must be changed to Fast or Slow.

When moving from an XC4000A to an XC4000E, use a speed grade two levels faster than the original speed grade (i.e., move an XC4000A-5 to an XC4000E-3, and an XC4000A-6 to an XC4000E-4). Although the majority of specifications are faster in the XC4000E than in the XC4000A, a few parameters are slower, so this conservative approach is recommended for a first pass. Use XDelay and simulation to verify performance prior to production.

If converting to an XC5200-family device, more significant changes may be required, and schematics will probably require changes. The most significant difference between the XC5200 and the XC4000A is that the XC5200 does not include RAM (see Table 2). For designs without RAM, the XC5200 is probably the most economical choice. Another difference is that the XC5200 does not have input or output flip-flops in the IOBs. Schematics including input and output flip-flops or latches must be changed to use standard flip-flops in the internal CLB array. Wide edge decoders are also not provided. Instead, the XC5200 includes general-purpose cascade circuits that can be used to implement decoder logic. Schematic alterations are required. There are other differences between the families, as well. These are described in detail in the Xilinx Application Note, "Design Migration From XC4000 to XC5200," available on the Xilinx WebLINX at http://www.xilinx.com. This application note also includes details of the software steps used in the conversion process that may also be useful when converting to the XC4000E.

When moving from an XC4000A to an XC5200, use a speed grade one level faster than the original speed grade for the first pass (i.e., move an XC4000A-5 to an XC5200-4, and an XC4000A-6 to an XC5200-5). Use XDelay and simulation to verify performance prior to production.

Fortunately, with the Xilinx Unified Libraries, most components in a schematic apply equally well to all Xilinx families. However, components using the features discussed above will need to be replaced.