Period and Two-Phase Clocks
The allowed path delay will automatically be reduced if a two-phase clock is detected
- If PERIOD does not have a “HIGH” or “LOW” keyword to define duty-cycle, then allowed path delay will be cut in half
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Timing constraint: NET "clock" PERIOD = 45 nS HIGH 50.000 % ;
2 items analyzed, 0 timing errors detected.
Minimum period is 8.586ns.
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Slack: 18.207ns path qneg_buf to qneg_buf relative to
22.500ns delay constraint (two-phase clock)
Path qneg_buf to qneg_buf contains 2 levels of logic:
Path starting from Comp: CLB_R1C7.K (from clock_buf)
To Delay type Delay(ns) Physical Resource
------------------------------------------------- --------
CLB_R1C7.XQ Tcko 1.830R qneg_buf
CLB_R1C7.C2 net (fanout=2) 0.543R qpos_buf
CLB_R1C7.K Thh1ck 1.920R qneg_buf
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Total (3.750ns logic, 0.543ns route) 4.293ns (to clock_buf)
45ns is the maximum allowed PERIOD declared in the UCF
“Two-phase clock” is indicated here
This indicates the magnitude of the path delay between
flops. There is no “adjustment” to this figure.
This indicates that the worst-case period for this
ENTIRE spec is 8.586ns (4.293ns x 2). If there had been a
single-phase path in this PERIOD spec that was 9ns, it would
have been reported as the worst-case value, if it were 8ns, it
This is the remaining slack (45ns/2 - 4.293ns = 18.207ns).
TRCE cut the spec in half (45ns/2=22.5ns) for this path