The Configuration Problem Solver

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Has the CCLK stopped running?

Yes, the CCLK has stopped. No, the CCLK continues to run.

Though in the Master Parallel Mode the FPGA uses the address bus A<17:0> to access the 8 bit wide configuration data, the FPGA also transitions the CCLK one cycle per configuration bit loaded into the device. If the CCLK was specified as the startup clock (default) in the design implementation then after the release of DONE at most only three (3) more CCLK cycles should be observed to complete the Startup Sequence. After which the CCLK should park high. If a "USER" clock was specified as the startup clock then the CCLK will not stop until the USER clock has finished the Startup sequence.