The Configuration Problem Solver
Do the Address pins toggle after a restart of configuration?
In the Master Parallel Mode the Address pins A<17:0> of the FPGA provide address data to access 8 bit wide data from a memory element. These pins should transition, either incrementing or decrementing, every 8 CCLKs. Probe the LSB address pin A0 to determine if these pins are active. |
HISTORY |
Family: XC4000 |
Mode: Master Parallel |
DONE: LOW |
INIT: HIGH |