The Configuration Problem Solver
Has the CCLK stopped running?
If the CCLK was specified as the startup clock (default) in the design implementation then after the release of D/P at most only three (3) more CCLK cycles should be observed to complete the Startup Sequence. After which the CCLK should park high. If a "USER" clock was specified as the startup clock then the CCLK will not stop until the USER clock has finished the Startup sequence. |
HISTORY |
Family: XC3000 |
Mode: Master Serial |
D/P: HIGH |
LDC: LOW |