Trading “Area” for “Performance”

Area (Free Transistors)

Time

DSP Processors: Sequential Processing

5 nsec

500 nsec

Processor requires a

? GHz Clock

for equivalent performance

200

MHz

Clock

X +

FPGA: Parallel Processing

X +

X +

Multiply Accumulates

This is how FPGAs harness Moore’s law.

Parallel processing give you the freedom to trade area (transistors) for performance. Hundreds of multiply accumulate operations can be performed in parallel in an FPGA. To obtain equivalent performance in a DSP processor requires a clock speed of many GHz.