The Configuration Problem Solver

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Address Pins don't start at 000000h.

To configure in the Master Parallel Mode the Mode Pins <M2:M1:M0> must be set to <100> for Parallel Up Mode, and <110> for Parallel Down Mode. In the Parallel Up Mode the Address lines start at <00000h> and count up. In the Parallel Down Mode the Address lines start at <1FFFFh> and count down.

If using the Parallel Up Mode on an XC4000EX (only) then by defualt there are 18 Address lines (A0..A17). However, there are also 4 additional and optional Address lines (A18..A21). These extra address lines are enabled with a BitGen option. Thus, the FPGA won't activate these extra Address lines until the control bit in the bitstream is loaded. Before these lines are activated they are disabled and pulled UP. Therefore, the address count would begin with 3E0000h instead of 000000h and is probably trying to access the Configuration data from the wrong address in the EPROM.

A PullDown resistor(s) must be added to these lines to correct this.