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The Configuration Problem Solver
CONCLUSION
The STARTUP Sequence has not completed.
The clock signal that is used for the STARTUP state machine is the CCLK by default. However, another (USER) clock may be specified by using the STARTUP component in the design and selecting the startup clock options for bitstream generation. Be sure which has been selected for your design implementation and assert the clock. See also the related answers. |
| HISTORY |
| Family: XC5200 |
| Mode: Master Parallel |
| DONE: HIGH |
| LDC: LOW |
| CCLK: RUNNING |