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The Configuration Problem Solver
CONCLUSION
Your FPGA should be properly configured and active.
Even though the LDC is Low, if the CCLK has stopped, then the FPGA has completed all four cycles of the Startup sequence. It may be that the LDC is Low due to design functionality. If the FPGA does not seem to be functioning see the related answers. |
| HISTORY |
| Family: SPARTAN |
| Mode: Master Serial |
| DONE: HIGH |
| LDC: LOW |
| CCLK: STOP |