The Configuration Problem Solver

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CONCLUSION

Either the DONE pin is being held low externally, or the STARTUP Sequence has not completed.

The DONE pin is possibly being held low externally, or is not being pulled up. The DONE pin is an Open-Drain driver that must be pulled up to achieve a logic high. While the FPGA does have a programmable internal pullup resistor to the DONE pad, we recommend using an external 4.7Kohm resistor. If necessary, seperate the DONE pin from the board to verify if an external source is holding it low.

Another possibility is that the Startup sequence could not be completed with the Startup options selected. By default, the CCLK is used to complete Startup and the DONE pin is released first in the sequence. The configuration options allow for a USER clock to be specified for the Startup sequence. In order for LDC to be High and DONE Low as a result of an incomplete Startup, the OUTputsActive would have to be set to be released by CCLK (C1, C2, C3) and the DONEactive set for a USER clock (U1, U2, etc). Rerun the Bitgen program with the correct startup options.

See also the related answers.

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