The Configuration Problem Solver

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Timing violations and clock glitches.

Verify that the Setup and Hold timing for the data to the clock meet the specifications in the Data Book. Another problem could be glitching on the clock line. Try adding a decoupling capacitor to the clock line to filter out high frequency noise. A 50 pF cap should be sufficient. If the glitching is in the very high frequency range then the capacitance of an oscilloscpe probe may actually be enough to mask it. Try restarting the configuration while probing the CCLK line.