The Configuration Problem Solver

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The Mode Pins are set incorrectly.

To configure in the Asynchronous Peripheral Mode the Mode Pins <M2:M1:M0> must be <101>. While these pins use the TTL standard threshold values (VIHmin=2.4 Volts and VILmax=0.8 Volts) make sure that these pins show strong logic `1's (4~5 Volts) and Logic `0's (<0.5 Volts). Measure these pins at the actual FPGA package to insure there aren't any connection errors on the board. If these pins were left unconnected add external pullup and pulldown resistors. DO NOT LEAVE MODE PINS FLOATING. Although Xilinx FPGAs have internal pullup resistors on the Mode pins, the strength of these pullups are not tested.