The Configuration Problem Solver

The CCLK is not transitioning or is not correctly connected.

    Probe the CCLK Pin directly at the FPGA package pin. Verify that the clock is indeed transitioning and is well within the timing specifications (< 8MHz) and is reaching the FPGA's pin. Probing a trace or the clock source is not proof positive that the signal is reaching the FPGA.

HISTORY
Family: SPARTAN
Mode: Slave Serial
DONE: LOW
INIT: HIGH
LDC: LOW
DOUT: NO