The Configuration Problem Solver

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The Mode Pins are set incorrectly.

To configure in the Master Serial Mode the MODE Pin must be a logic high <0>. While this pin uses the TTL standard threshold values (VILmax=0.8 Volts) make sure that these pins show a good strong logic `0' (<0.5 Volts). Measure the MODE pin at the actual FPGA package to insure there aren't any connection errors on the board. If this pin was left unconnected add an external pullup resistor. Although Xilinx FPGAs have an internal pullup resistor on the MODE pin, the strength of this pullup is not tested.