The Configuration Problem Solver

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The Mode Pins are set incorrectly.

To configure in the Master Serial Mode the Mode Pins <M1:M0> must be <10>. While these pins use the LVTTL standard threshold values make sure that these pins show a good strong Logic '1' and Logic '0' (~3 and <0.5 Volts, respectively). Measure the MODE pins at the actual FPGA package to insure there aren't any connection errors on the board. If the M0 pin was left unconnected add an external pullup resistor. Although Xilinx FPGAs have an internal pullup resistor on the MODE pin, the strength of this pullup is not tested.