The Configuration Problem Solver

The CCLK is not transitioning or is not correctly connected.

    Probe the CCLK Pin directly at the FPGA package pin as well as it's destination pin. Verify that the clock is indeed transitioning and is well within the timing specifications for the clock load. If the CCLK was set for FAST try resetting it to SLOW in the configuration options.

HISTORY
Family: SpartanXL
Mode: Master Serial
DONE: LOW
INIT: HIGH
LDC: LOW
DOUT: NO