The Configuration Problem Solver

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The Mode Pins are set incorrectly.

To configure in the Master Serial Mode the Mode Pins M2 M1 and M0 must all be to a logic Low <000>. The Mode pins use the TTL standard threshold values (VILmax=0.8 Volts). Make sure that these pins show a good strong logic `0' (<0.5 Volts). Measure these pins at the actual FPGA package to insure there aren't any connection errors on the board. If these pins were left unconnected add external pulldown resistors. Xilinx FPGAs have internal pullup resistors on the Mode pins, the strength of these pullups are not tested. Some may be stronger than others. A pulldown strength of 1Kohm is recommended.